1. Field of Invention
This invention relates to a semiconductor structure and fabrication of the same. More particularly, this invention relates to a method of fabricating a hybrid orientation substrate and a structure of a hybrid orientation substrate that can be fabricated with the same method.
2. Description of Related Art
As the requirements on the integration degree and speeds of integrated circuits unceasingly get higher, the dimensions of semiconductor devices are reduced rapidly, and certain ways other than the dimension reduction to improve the device speed have been studied. For example, the strained silicon technology and the hybrid crystal orientation technology have been frequently applied in many processes.
The strained silicon technology features causing a compressive or tensile strain in a silicon layer to enhance the mobility of holes or electrons and thereby improve the device speed. A channel region of strained silicon may be formed by forming the hard mask layer for defining the trench of device isolation as a compressive or tensile stress layer. The strain in the channel can be retained after the hard mask layer is removed.
On the other hand, the hybrid crystal orientation technology features areas of two different crystal orientations on a single silicon wafer. The two orientations are usually <100> and <110>, because the electron mobility is higher in <100> silicon and the hole mobility in <110> silicon is 2-4 times higher than that in <100> silicon. One method to form a hybrid orientation substrate with a trench isolation structure thereon is based on the amorphization/templated recrystallization (ATR) approach, which is applied to a direct-silicon-bonded (DSB) wafer that includes a <100> silicon substrate and a <110> silicon layer directly thereon. Selected portions of the <110> silicon layer are first amorphized with ion implantation after a trench isolation structure is formed, and then a solid-phase epitaxy (SPE) process is performed to convert the amorphized silicon to <100> silicon based on the <100> silicon of the underlying substrate.
However, a portion of the amorphized silicon at the trench corners cannot be converted to <100> silicon but forms trench-edge defects. There are also defects formed near the interface between the substrate and the recrystallized layer. Thus, the devices formed on the recrystallized layer including NMOS transistors do not have good reliability.
To prevent the trench-edge defects, U.S. Patent Application Publication No. 2005/0116290 provides an improved method that performs the SPE process after the trench of the trench isolation is formed but before the same is filled with an insulating material, so as to achieve a complete recrystallization of the amorphized silicon.
On the other hand, to eliminate the defects formed near the interface between the silicon substrate and the recrystallized silicon, U.S. Patent Application Publication No. 2006/0154429 provides an improved method that adds high-temperature annealing at 1200-1400° C. particularly after the above SPE process to rearrange the silicon atoms.